1. Technical Field
The present invention relates to a memory device, and more particularly, the present invention relates to a nonvolatile memory device and a read method for the nonvolatile memory device.
2. Discussion of the Related Art
Semiconductor memory devices are roughly classified into volatile memories such as DRAM, SRAM, and the like and non-volatile memories such as EPROM, FRAM, PRAM, MRAM, flash memory, and the like. Volatile memories lose contents stored therein at power-off, while non-volatile memories retain contents stored therein even at power-off. In particular, since flash memories are able to be programmed at a relatively high program speed, with low power consumption, and may be used to store a relatively large quantity of data, they have been widely used as storage medium of computer systems.
A flash memory has a memory cell array which stores data. The memory cell array consists of a plurality of memory blocks, each of which is divided into a plurality of pages. Each of the pages consists of a plurality of memory cells. In the flash memory, an erase operation may be performed one full block at a time and a write or read operation may be performed one full page at a time.
Memory cells in a flash memory may be either “ON” cells or “OFF” cells based upon their threshold voltages. The ON cells store data ‘1’ and are called an ‘erase cell’. The OFF cells store data ‘0’ and are called a ‘program cell’. The ON cells have a threshold voltage between −3V and −1V, and the OFF cells have a threshold voltage between +1V and +3V.
A flash memory includes cell strings (refer to FIG. 2), each of which includes a string select transistor connected to a string select line SSL, memory cells each connected to corresponding word lines WL0 to WL31, and a ground select transistor connected to a ground select line GSL. The string select transistors in the respective strings are connected to corresponding bit lines BL, and the ground select transistors therein are connected in common to a common source line CSL.
At a read operation, a selected word line is supplied with a select read voltage Vrd, and unselected word lines are supplied with an unselect read voltage Vread. Herein, the unselect read voltage Vread is a voltage high enough to turn on memory cells connected with unselected word lines.
An erroneous read operation in which cells programmed to an ON cell (data ‘1’) are read as an OFF cell (data ‘0’) may be referred to herein as a “read fail.” A read fail may arise due to various causes at the read operation of a flash memory.
An example of one cause of a read fail is charge leakage. The read fail due to the charge leakage may arise when charge stored in a programmed cell is leaked into a channel. If the read fail arises due to charge leakage, a threshold voltage distribution of OFF cells programmed with data ‘0’ is shifted into a threshold voltage distribution of ON cells (refer to FIG. 4).
If the charge leakage is sufficiently seriously, data stored in memory cells may be changed fully. For example, if the charge leakage arises to the extent that threshold voltages of programmed memory cells are lowered below a select read voltage Vrd (e.g., 0V), memory cells programmed with data ‘0’ may be read as data ‘1’. The read fail due to charge leakage may arise frequently in Multi-Level Cell (MLC) flash memories capable of storing multi-bit data in each cell.